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Analog Frequency Multiplier
VCXO Family of Products
PRODUCT DESCRIPTION PhaseLink's Analog Frequency Multiplier TM (AFMs) are the industry's first `Balanced Oscillator' utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase locked loop, in CMOS technology. PhaseLink's patent pending PL56X family of AFM products can achieve up to 800 MHz output frequency with practically no jitter or phase noise deterioration. In addition, the low frequency input crystal requirement makes the AFMs the most affordable high performance timing source in the market. PL560-XX family of products utilize a low-power CMOS technology and are housed in a 16-pin (T)SSOP, and 16-pin 3x3 QFN. FEATURES * * * * * * Non Phase Locked Loop frequency multiplication Input frequency from 30-200 MHz Output frequency from 60-800-MHz Low Phase noise and jitter (equivalent to fundamental crystal at the output frequency) Unbeatably low jitter o RMS phase jitter < 0.25ps (12kHz-20MHz) o RMS period jitter < 2.5 ps Low Phase Noise o -142 dBc/Hz @100kHz Offset from 155.52MHz o -150 dBc/Hz @10MHz Offset from 155.52MHz High linearity pull range (typ. 5%) +/- 120 PPM pullability VCXO Low input frequency eliminates the need for expensive crystals Differential output levels (PECL, LVDS), or singleended CMOS Single 2.5V or 3.3V +/- 10% power supply Optional industrial temperature range (-40C to +85C) Available in 16-pin (T) SSOP, and 3x3 QFN
* * * * * * *
Figure 1: 2x AFM Phase Noise at 311.04MHz
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Analog Frequency Multiplier
VCXO Family of Products
L2X OECTRL X IN
O s c illa to r A m p lifie r F re q u e n c y X2 F re q u e n c y X4
VC on
QBAR Q
XOUT O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Overall VCXO AFM Block Diagram
Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Jitter Histogram at 311.04 MHz Analog Frequency Multiplier (2x) with 155.52MHz crystal Figure 4: Spectrum Analysis at 311.04 MHz Analog Frequency Multiplier (2x) with sub-harmonic below -72 dBc
OE LOGIC SELECTION OUTPUT OESEL
0 (Default) PECL 1 0 (Default) LVDS or CMOS 1
OE
0 (Default) 1 0 1 (Default) 0 1 (Default) 0 (Default) 1
Output State
Enabled Tri-state Tri-state Enabled Tri-state Enabled Enabled Tri-state
OESEL and OE: Connect to VDD to set to "1", connect to GND to set to "0". Internally set to default through pull-down / -up.
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Analog Frequency Multiplier
VCXO Family of Products
PRODUCT SELECTION GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Part Number
Input Frequency Range (MHz)
Analog Frequency Multiplication Factor 4 4 4 4 4 2 2 2 2 2
Output Frequency Range (MHz)
Phase Noise AT Frequency Offset From Carrier (dBc/Hz) Output Type Carrier Freq. (MHz) 622.08 622.08 155.52 155.52 155.52 155.52 155.52 155.52 311.04 311.04 10 KHz -130 -130 -128 -128 -128 -138 -138 -138 -135 -135 100 KHz -137 -137 -142 -142 -142 -142 -142 -142 -142 -142 10 MHz -150 -150 -150 -150 -150 -149 -149 -149 -151 -151
10 Hz -55 -55 -50 -50 -50 -65 -65 -65 -60 -60
100 Hz -85 -85 -82 -82 -82 -95 -95 -95 -85 -85
1 KHz -110 -110 -110 -110 -110 -122 -122 -122 -112 -112
1 MHz -148 -148 -148 -148 -148 -148 -148 -148 -150 -150
PL560-08 PL560-09 PL560-37 PL560-38 PL560-39 PL560-47 PL560-48 PL560-49 PL560-68 PL560-69
75 - 200 75 - 200 30 - 80 30 - 80 30 - 80 30 - 80 30 - 80 30 - 80 75 - 200 75 - 200
300 - 800 300 - 800 120 - 320 120 - 320 120 - 320 60 - 160 60 - 160 60 - 160 150 - 400 150 - 400
PECL LVDS CMOS PECL LVDS CMOS PECL LVDS PECL LVDS
Phase Noise numbers were obtained using Agilent 5500.
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
Jitter Calc. Freq. (MHz) 622 622 155 155 155 155 155 155 311 311 RMS Period Jitter (Ps) Peak to Peak Period Jitter (Ps) RMS Accumulated (L.T.) Jitter (Ps) Phase Jitter (12 KHz-20MHz) (Ps) Typ. 0.09 0.09 0.25 0.25 0.25 0.25 0.25 0.27 0.18 0.18 Spectral Specifications / Sub-harmonic Content (dB), Frequency (MHz) Carrier @ @ @ @ @ @ Max. Freq. -75% -50% -25% +25% +50% +75% (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) 622 622 155.52 155.52 155.52 155.52 155.52 155.52 311.04 311.04 -50 -50 -75 -75 -75 -50 -50 -62 -62 -62 -68 -68 -68 -72 -72 -45 -45 -47 -47 -47 -47 -65 -65 -65 -68 -68 -68 -85 -85 -55 -55 -75 -75 -75
Part Number
Min. Typ. Max. Min. Typ. Max. Min. Typ. 4 4 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 6 6 3 3 3 3 3 3 3 3 25 25 18 18 18 18 18 18 18 18 30 30 20 20 20 20 20 20 20 20
Max. Min. 6 6 3 3 3 3 3 3 3 3
PL560-08 PL560-09 PL560-37 PL560-38 PL560-39 PL560-47 PL560-48 PL560-49 PL560-68 PL560-69
Note: Wavecrest Data 10,000 hits. No Filtering was used in Jitter Calculations. Agilent 5500 was used for Phase Jitter Calculations. Spectral Specifications were obtained using Agilent E7401A.
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Analog Frequency Multiplier
VCXO Family of Products
CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS BOARD LAYOUT CONSIDERATIONS
AFM IC XTA
XIN (Pin # 4) XOUT (Pin # 5)
AFM IC
XTAL
Ceramic SMD
XIN (Pin # 4) XOUT (Pin # 5)
To minimize parasitic effects, and improve performance: * Place the crystal as close as possible to the IC. * Make the board traces that are connected to the crystal pins symmetrical. * The board trace symmetry is important, as it reduces the negative parasitic effects, for a clean frequency multiplication with low jitter. Parasitic have negative effect on frequency pulling of a VCXO and jitter.
CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE CRYSTAL SPECIFICATIONS
PART NUMBER
CRYSTAL RESONATOR FREQUENCY (FXIN)
TUNING PERFORMANCE
ESR (RE)
Max. CRYSTAL FREQ (MHz) 155.52 5pF 30 155.52 30.72 1.8pF 2.8pF 4.5pF 5.1pF 5.3pF 2.0pF 5.7fF 12.4fF 19.1fF 20.9fF 25.6fF 6.7fF 316 228 236 242 207 305 -134 ppm -167ppm -163ppm -131ppm -157ppm -92ppm +87 ppm +176ppm +167ppm +98ppm +141ppm +110ppm
MOD E
CL (xtal)
CONDITIONS At Vcon = 1.65V TYP.
CRYSTAL
C0 3.0pF C1 12.2fF C0/C1 245
TUNING (Typical)
VC: 1.65V 0V -145 ppm VC: 1.65V 3.4V +108 ppm
PL560-08/09 PL560-68/69
75~200MHz
Fundamental
PL56037/38/39 PL56047/48/49
30~80MHz
Fundamental
At Vcon = 1.65V
30.72 5pF 30 38.88 38.88 77.76
Note: Non specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.
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Analog Frequency Multiplier
VCXO Family of Products
VOLTAGE CONTROL SPECIFICATION PARAMETERS
VCXO Stabilization Time VCXO Tuning Range CLK output pullability Linearity VCON input impedance VCON modulation BW 0V < VCON < 3.3V, -3dB 130 25
SYMBOL
TVCXOSTB
CONDITIONS
From power valid XTAL C0 /C1 <300 VCON= 1.65V 1.65V XTAL C0 /C1 <300
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
200 100 120
ppm
5
10
% k kHz
EXTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION The required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink's evaluation board design (Gerber file available upon request). These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the "AFM Tuning Assistant" software. You can download this software from PhaseLink's web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the `L2' inductor value, and the second worksheet (named L4) is used for fine tuning of the `L4' (used in 4x AFMs only) inductor value. For those designs using PhaseLink's recommended board layout, you can use the "AFM Tuning Assistant" to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink's board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure:
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Analog Frequency Multiplier
VCXO Family of Products
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE - Cinternal = Based on AFM Device - Cpad = 2.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, The following amplifier stage
PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 1.0 pF, Stray Capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if used
* There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of `AFM Tuning Assistant', respectively. * LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23. * Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used. * Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the `AFM Tuning Assistant' software to calculate L2X (and C2X if used) for your resonance frequency. * For 4X AFMs, repeat the same procedure in the L4X worksheet. * See the examples below.
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Analog Frequency Multiplier
VCXO Family of Products
DETERMINING STRAY L's AND C's IN A LAYOUT
Figure 5: Diagram Representation of the Board Layout
Lets take the PL560-38 (4x VCXO) for example. This takes a crystal input range of 30 to 80 MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L's and C's of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz). 120 MHz AFM Tuning: Using the "AFM Tuning Assistant" find the PL560-3x in the L2x worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4x at 120 MHz. Results: L2X = 180 nH, L4X = 82 nH. 320 MHz AFM tuning: Repeat the previous procedure for L2x at 120 MHz and L4x at 320 MHz. Results: L2X = 24 nH, L4X = 10 nH. Proceed and assemble the test units. Measuring 120 MHz L2x: Connect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3v pk-pk amplitude. Vary the generator above and below 30 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak accorded at 29.8x2 or 59.6 MHz.
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Analog Frequency Multiplier
VCXO Family of Products
Measuring 320 MHz L2x: Connect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3v pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak accorded at 78.0 x 2 = 156 MHz In the AFM Tuning Assistant, add the scope's probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2x value with 180 nH and see if it peaks at 59.6 MHz. IF it it does not, adjust the Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2x and fine tune LWB1 for 156 MHz. Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray) Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray)
Internal Capacitor Selection by Device Device Number
2X P560-0X P560-3X P560-4X P560-6X 7.625 34.125 34.125 7.625
Cinternal (pF)
4X 6.250 16.500
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Analog Frequency Multiplier
VCXO Family of Products
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
VDD VI VO TS TA TJ
MIN.
VSS-0.5 VSS-0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 +85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
PECL ELECTRICAL CHARACTERISTICS PARAMETERS
Supply Current (with loaded outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current Output High Voltage Output Low Voltage Clock Rise Time Clock Fall Time VOH VOL tr tf @20/80% @80/20% 0.25 0.25 RL = 50 to (VDD - 2V) VDD - 1.025 VDD - 1.620 0.45 0.45
SYMBOL
IDD VDD
CONDITIONS
Fout = 622.08
MIN.
2.25
TYP.
75
MAX.
80 3.63 55
UNITS
mA V % mA V V ns ns
@ Vdd - 1.3V
45
50 50
PECL Transistion Time Waveform
DUTY CYCLE
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
45 - 55%
55 - 45%
OUT 50 2.0V 50% 80% 50% 20% 50 OUT OUT tSKEW OUT tR tF
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Analog Frequency Multiplier
VCXO Family of Products
LVDS ELECTRICAL CHARACTERISTICS PARAMETERS
Supply Current (with loaded outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current Differential Clock Rise Time Differential Clock Fall Time VOD VOD VOH VOL VOS VOS IOXD IOSD tr tf RL = 100 CL = 10 pF (see figure) 0.2 0.2 Vout = VDD or GND VDD = 0V RL = 100 (see figure) 247 -50 1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7 0.5 0.5 1.375 25 10 -8 0.7 0.7
SYMBOL
IDD VDD
CONDITIONS
Fout = 622.08, LVDS
MIN.
TYP.
55
MAX.
60 3.63
UNITS
mA V % mA
2.97 @ 1.25V (LVDS) 45 50 50 355
55
454 50 1.6
mV mV V V V mV A mA ns ns
LVDS Transistion Time Waveform LVDS Levels Test Circuit
OUT
LVDS Switching Test Circuit
OUT
OUT 0V (Differential) OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100 VDIFF 0V 20%
80%
80%
50 CL = 10pF OUT OUT
20%
tR
tF
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Analog Frequency Multiplier
VCXO Family of Products
CMOS ELECTRICAL CHARACTERISTICS PARAMETERS
Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output High Voltage Output Low Voltage Output High Voltage at CMOS level Output drive current Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current
SYMBOL I DD V DD
VOH VOL VOHC
CONDITIONS
At 100MHz, load=15pF
MIN.
TYP.
16
MAX.
20 3.63
UNITS
mA
2.25 IOH = -8.5mA IOL = 8.5mA IOH = -4mA VOL = 0.4V, VOH = 2.4V (per output) 10% ~ 90% VDD with 10 pF load Measured @ 50% VDD 45 VDD- 0.4 8.5 1.2 50 50 2.4
V
V
0.4
V V
I OSD
Tr/Tf
mA 1.6 55 ns % mA
IS
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Analog Frequency Multiplier
VCXO Family of Products
BOARD LAYOUT DESIGN CONSIDERATIONS FOR AFMs
L2x and L4x: Try to reduce the PCB trace inductance to a minimum by placing L2x and L4x as physically close to their respective pins as possible. Also be sure to bypass each Vdd connection especially taking care to place a 0.01 uF bypass at the Vdd side of L2x and L4x (See recommended layout). Crystal connections: Be sure to keep the ground plane under the crystal connections continuous so that the stray capacitace is consistent on both crystal connections. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection pins of the IC. If you chose to use a series capacitance and or inductor to fine tune the crystal frequency be sure to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout). Even if one of the capacitors with be a 0.01 uf and the other is used to tune the frequency. And to further maintain a symmetrical balance on a crystal that may have more internal Cstray on one pin or the other. Place capacitor pads (Cbal) on each crystal lead to ground (see recommended layout). You can refer to (xxx) if tuning of Cbal is required. R3rd is only required if a 3 rd overtone crystal is used. Vdd and Gnd: Bypass VDDANA and VDDBUF with separate bypass capacitors and if a Vdd plane is used feel each bypass cap with its own via. And be sure to connect any ground pin including the bypass caps with short via connection to the ground plane. OESEL: J1 is recommended so the same PCB layout can be used for both Output Enable low (No J1) or Output Enable high (J1 = ohms) if this function is chosen.
Note: Please contact PhaseLink for the Gerber files of the board layouts.
4X Layout
2X Layout
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Analog Frequency Multiplier
VCXO Family of Products
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
GNDBUF
OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL DNC GNDANA 1 2 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 L2X VDDOSC OESEL VDDANA VDDBUF QBAR Q
OSCOFFSEL GNDOSC 1 2 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 L2X VDDOSC OESEL VDDANA VDDBUF QBAR Q
3 4 5 6 7 8
VDDANA OESEL VDDOSC L2X
13 14 15 16
12
11
10
9
8 7 6 5
GNDANA DNC OECTRL XOUT
VCON XIN XOUT OECTRL L4X
3 4 5 6 7 8
VDDANA OESEL VDDOSC L2X
13 14 15 16
12
11
10
GNDBUF
9
VDDBUF
VDDBUF
QBAR
QBAR
Q
Q
OSCOFF SEL GNDOSC
OSCOFF SEL GNDOSC
XIN
GNDBUF
VCON
VDDOSC
GNDBUF
2X AFM Package Pin Out
4X AFM Package Pin Out
PIN ASSIGNMENTS
Name
OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL DNC L4X 7 I
Pin#
1 2 3 4 5 6
Type
I P I I O I
Product
2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X 4X
Description
Set to "0" (GND) to choose to turn off the oscillator when outputs are disabled (OE). Default (no connect) is OSC always on. GND connection for oscillator circuitry. Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. Input from crystal oscillator circuitry. Output from crystal oscillator circuitry. Output Enable input (see "OE LOGIC SELECTION TABLE"). Do Not Connect. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This inductor is used with 4X AFMs. GND connection. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. GND connection for output buffer circuitry. PECL/LVDS or CMOS output. Complementary PECL/LVDS output or in phase CMOS. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic (see "OE SELECTION TABLE". VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q.
GNDANA 8 VDDOSC GNDBUF Q QBAR VDDBUF VDDANA OESEL VDDOSC L2X 9 10 11 12 13 14 15 16 P O O P P I P I P
2X 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X
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VCON
XIN
PLL560-4X
PLL560-0X
8 7 6 5
VDDOSC L4X OECTRL XOUT
P560-4X
1 2 3 4
P560-0X
1 2 3 4
Analog Frequency Multiplier
VCXO Family of Products
PACKAGE INFORMATION 16 PIN SSOP
16 PIN SSOP ( inch )
SSOP Symbol A A1 B C D E H L e Min. .053 .004 .008 .007 .189 .150 .228 .016 Nom. .064 .006 .193 .154 .236 .025 .025 BASIC Max. .069 .010 .012 .010 .197 .157 .244 .050 A1 B C L e D E H
A
16 PIN 3x3 QFN
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Analog Frequency Multiplier
VCXO Family of Products
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
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PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PL560-XX
PART NUMBER
XX
TEMPERATURE C= COMMERCIAL I= INDUSTRIAL PACKAGE TYPE O=TSSOP Q=QFN 3x3 X=SSOP
Order Number PL560-XXOC-R PL560-XXQC-R PL560-XXXC-R PL560-XXOC PL560-XXQC PL560-XXXC
Marking P560-XX P560-XX P560-XX P560-XX P560-XX P560-XX OC QC XC OC QC XC
Package Option TSSOP - Tape and Reel QFN - Tape and Reel SSOP - Tape and Reel TSSOP - Tube QFN - Tube SSOP - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
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